`include "include.v"

module clk_blk (
  input  wire CLKIN_IN,
  input  wire RST_IN,
  output wire CLK0_OUT,
  output wire CLK180_OUT,
  output wire LOCKED_OUT
);

reg clk0_out_r;
reg clk180_out_r;

assign CLK0_OUT   = clk0_out_r;
assign CLK180_OUT = clk180_out_r;
assign LOCKED_OUT = ~RST_IN;

// clk0_out is clkin_in
// clk180_out is ~clkin_in
always @(posedge CLKIN_IN or posedge RST_IN) begin
  if (RST_IN) begin
    clk0_out_r   <= 1'b0;
    clk180_out_r <= 1'b1;
  end else begin
    clk0_out_r   <= ~clk0_out_r;
    clk180_out_r <= ~clk180_out_r;
  end
end

endmodule  
